The expanded direct memory access processor is the subject of U.S. patent application Ser. No. 09/713,609, filed Nov. 15, 2000, entitled REQUEST QUEUE MANAGER IN TRANSFER CONTROLLER WITH HUB AND PORTS. An expanded direct memory access processor is an interconnection network which assumes the task of communication throughout the processor system and its peripherals in a centralized function. Within the expanded direct memory access processor, a system of a main hub and ports tied together by multiple pipelines is the medium for all data communications among processors and peripherals.
The hub interface unit is of generic design. This hub interface unit is made identical for all ports, whether the attached application unit operates at the high frequency of the core processor or the much lower frequency of a some types of relatively slow peripherals. The application unit includes a variety of external port interfaces of customized design with considerable variation their internal make-up.
This invention relates to the novel aspects of a configuration bus interconnection protocol. This configuration bus interconnection protocol loads memory-mapped registers in various portions of the digital signal processor chip. Integrated circuits including an expanded direct memory access processor can utilize a configuration bus to configure the control registers throughout the external ports. Configuration takes place normally as a prelude to application usage through boot up or initialization processes. It is also possible that a device using a configuration bus of this invention could be re-configured dynamically during application usage under program control.
The configuration bus is a parallel set of communications protocols used for control of peripherals rather than for data transfer. While the expanded direct memory access processor is heavily optimized for maximizing data transfers, the configuration bus protocol and configuration bus interface is designed for simplicity, ease of implementation and portability. The configuration bus signals are of uniform definition for all application unit interfaces. The ability of the uniformly defined configuration bus to interface with a wide variety of customized peripheral units is a key feature of the invention.